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Espressif Systems /ESP32-P4 /HP_SYS /CORE_TIMEOUT_INT_CLR

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Interpret as CORE_TIMEOUT_INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CORE0_AHB_TIMEOUT_INT_CLR)CORE0_AHB_TIMEOUT_INT_CLR 0 (CORE1_AHB_TIMEOUT_INT_CLR)CORE1_AHB_TIMEOUT_INT_CLR 0 (CORE0_IBUS_TIMEOUT_INT_CLR)CORE0_IBUS_TIMEOUT_INT_CLR 0 (CORE1_IBUS_TIMEOUT_INT_CLR)CORE1_IBUS_TIMEOUT_INT_CLR 0 (CORE0_DBUS_TIMEOUT_INT_CLR)CORE0_DBUS_TIMEOUT_INT_CLR 0 (CORE1_DBUS_TIMEOUT_INT_CLR)CORE1_DBUS_TIMEOUT_INT_CLR

Description

interrupt clear register

Fields

CORE0_AHB_TIMEOUT_INT_CLR

Write 1 to clear hp_core0_ahb_timeout int
CORE1_AHB_TIMEOUT_INT_CLR

Write 1 to clear hp_core1_ahb_timeout int
CORE0_IBUS_TIMEOUT_INT_CLR

Write 1 to clear hp_core0_ibus_timeout int
CORE1_IBUS_TIMEOUT_INT_CLR

Write 1 to clear hp_core1_ibus_timeout int
CORE0_DBUS_TIMEOUT_INT_CLR

Write 1 to clear hp_core0_dbus_timeout int
CORE1_DBUS_TIMEOUT_INT_CLR

Write 1 to clear hp_core1_dbus_timeout int

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data